The entire disclosure including the specifications, claims, drawings, and abstracts of Japanese patent applications Nos. Hei 9-313359, filed on Nov. 14, 1997 and Hei 9-313360, filed on Nov. 14, 1997 is incorporated herein by reference.
This invention relates to non-volatile semiconductor memory using ferroelectric capacitors, and more specifically to a semiconductor memory comprising ferroelectric memory FETs each having at least a ferroelectric layer between a gate electrode and a semiconductor layer, and to a method of gaining access to the semiconductor memory.
A ferroelectric memory has for example an FET structure as shown in FIG. 14 in which a ferroelectric layer 54 and a gate electrode 55 are provided on part of a semiconductor substrate 51 between a drain region 52 and a source region 53 formed on a semiconductor substrate 51. It is known that; when a high voltage is applied between the gate electrode 55 and the semiconductor substrate 51, polarization charge is produced, and xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is written depending on the direction of polarization; the data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d can be read by applying a low voltage to the gate electrode; and the data do not disappear even if power is turned off. Therefore it is known that the device can be used as a non-volatile memory of non-destructive reading type. However, practical use of a memory is yet to be realized in which the above-described memory cells are arranged as a matrix circuit. That is, a method is known in which each of cells arranged as a matrix may be accessed through selection elements provided, two for each cell, one for writing and the other for reading. However, when two selection elements are used for each cell respectively, a problem arises that the cell area increases and the degree of integration extremely decreases.
On the other hand, an access method is considered for example for a memory made of matrix-arranged ferroelectric capacitors, in which a power source voltage Vcc is equally divided into three and applied to each line, in order to prevent a voltage from being applied to a cell other than an intended, selected cell at the time of writing for example and prevent the data from being rewritten. To apply the three equally divided voltage application method to a memory in which ferroelectric memory FETs are arranged as a matrix, the following access method may be considered.
That is, as shown in the simplified drawing FIG. 13(a), in the case cells comprising a plurality of ferroelectric memory FETs in matrix-pattern are wired and xe2x80x9c1xe2x80x9d is to be written to a selected cell P, the writing is carried out by applying Vcc to a word line WL1 on which the selected cell P is present, ⅓ of Vcc to a word line WL2 on which the selected cell P is absent, 0 to a bit line BL1 on which the selected cell P is present, and ⅔xc2x7Vcc to a bit line BL2 on which the selected cell P is absent. In the case xe2x80x9c0xe2x80x9d is to be written to the selected cell P, 0 is applied to the word line WL1, ⅔ of Vcc to the word line WL2, Vcc to the bit line BL1, and ⅓ of Vcc to the bit line BL2. When the selected cell P is to be read, V1 (a voltage lower than Vcc at the time of reading) is applied to the word line WL1, 0 to the word line WL2, 0 to the bit line BL1, and VSA (data detecting voltage) to a data line DL1. The sequence in writing and reading xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is shown in FIG. 13(b). The blank boxes in FIG. 13(b) denote that the corresponding lines are open or at 0 V. As a result, when the writing is carried out, a high voltage of Vcc or xe2x88x92Vcc is applied between the gate electrode and the semiconductor substrate to write xe2x80x9c1xe2x80x9d or xe2x80x9c0.xe2x80x9d At this time, the voltage applied to a cell not selected is ⅓ of Vcc or xe2x88x92⅓ of Vcc and writing is not carried out. At the time of reading, while V1 is applied between the gate electrode and the semiconductor substrate in selected cells, cells not selected are open or at 0 V, almost no voltage is applied, and no reading is carried out.
While writing and reading can be made by selecting only an intended cell as described above, at the time of writing for example, the voltage of ⅓ of Vcc is also applied to cells not selected. When the voltage ⅓ of Vcc is applied, polarization of ferroelectric capacitor (polarization corresponding to the stored data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) is disturbed. After repeated applications, there is a concern that the data stored in cells to which no writing is made may change. Under such a circumstance, there are following problems: For the small-sized semiconductor memories using the ferroelectric memory cells, an access method without disturbing the data stored in the memory cells not selected is yet to be established. And as described above, a semiconductor memory has not yet been put to practical use in which the ferroelectric memory FETs are arranged as a matrix of cells.
According to the invention, a semiconductor memory provided with ferroelectric layers, that includes memory cells, buffer cells, and buffer circuits. The memory cells each include a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer. The buffer cells are capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells. The buffer circuits are for transferring the data in the memory cells to the buffer cells and for further writing the transferred data again to the memory cells.
Also according to the invention, a semiconductor memory provided with ferroelectric layers, that includes a plural number of memory cells, buffer cells, and buffer circuits. The plural number of memory cells are arranged in a matrix each memory cell comprising a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer. The buffer cells are capable of storing data from at least one line of the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells. The buffer cells are ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer. The buffer circuits are for transferring the data in at least one line of the memory cells as a whole to the buffer cells and further writing the transferred data again to the memory cells. Each buffer circuit includes a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.
Further according to the invention, a semiconductor memory provided with ferroelectric layers, that includes memory cells, buffer cells, and buffer circuits. The memory cells each are a ferroelectric memory FET having a ferroelectric layer between a gate electrode and a semiconductor layer. The buffer cells are capable of storing data from the memory cells to prevent the data from being lost when a disturbing voltage is applied to the memory cells. The buffer cells are ferroelectric memory FETs each having a ferroelectric layer between a gate electrode and a semiconductor layer. The buffer circuits are for transferring the data in the memory cells to the buffer cells and for further writing the transferred data again to the memory cells. Each buffer circuit includes a first selection element for making connection between the gate electrode of each buffer cell and a data line of the memory cell to control the transfer of data from the memory cell, a second selection element connected to the gate side of the buffer cell to control the reading of data from the buffer cell, and a transformer connected to a bit line connecting substrates of the memory cells for converting the voltage of the data read from the buffer cell.
While the features of this invention can be broadly shown as described above, its constitution and contents together with its objects and other features will become further apparent from the following disclosure in reference to the appended drawings.